The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include spin-coating of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
Spin coating of photoresist on wafers, as well as the other steps in the photolithography process, is carried out in an automated coater/developer track system using wafer handling equipment which transport the wafers between the various photolithography operation stations, such as vapor prime resist spin coat, develop, baking and chilling stations. Robotic handling of the wafers minimizes particle generation and wafer damage. Automated wafer tracks enable various processing operations to be carried out simultaneously. Two types of automated track systems widely used in the industry are the TEL (Tokyo Electron Limited) track and the SVG (Silicon Valley Group) track.
Photoresist materials are coated onto the surface of a wafer by dispensing a photoresist fluid typically on the center of the wafer as the wafer rotates at high speeds within a stationary bowl or coater cup. The coater cup catches excess fluids and particles ejected from the rotating wafer during application of the photoresist. The photoresist fluid dispensed onto the center of the wafer is spread outwardly toward the edges of the wafer by surface tension generated by the centrifugal force of the rotating wafer. This facilitates uniform application of the liquid photoresist on the entire surface of the wafer.
After it is layered on the substrate, the photoresist is exposed to light through a mask or reticle in an alignment and exposure process. A reticle is a transparent plate patterned with a circuit image to be formed in the photoresist coating on the wafer. A reticle contains the circuit pattern image for only a few of the die on a wafer, such as four die, for example, and thus, must be stepped and repeated across the entire surface of the wafer. In contrast, a photomask, or mask, includes the circuit pattern image for all of the die on a wafer and requires only one exposure to transfer the circuit pattern image for all of the dies to the wafer. After alignment and exposure, the photoresist is developed.
The circuit pattern defined by the developed and hardened photoresist is next transferred to the underlying metal conductive layer using a metal etching process, in which metal over the entire surface of the wafer and not covered by the cross-linked photoresist is etched away from the wafer with the metal under the cross-linked photoresist that defines the circuit pattern protected from the etchant. As a result, a well-defined pattern of metallic microelectronic circuits which closely approximates the cross-linked photoresist circuit pattern remains in the metal layer.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner.
A typical method of forming a circuit pattern on a wafer includes introducing the wafer into the automated track system and then spin-coating a photoresist layer onto the wafer. The photoresist is next cured by conducting a soft bake process. After it is cooled, the wafer is placed in an exposure apparatus, such as a stepper, which aligns the wafer with an array of die patterns etched on the typically chrome-coated quartz reticle. When properly aligned and focused, the stepper exposes a small area of the wafer, then shifts or “steps” to the next field and repeats the process until the entire wafer surface has been exposed to the die patterns on the reticle. The photoresist is exposed to light through the reticle in the circuit image pattern. Exposure of the photoresist to this image pattern cross-links and hardens the resist in the circuit pattern. After the aligning and exposing step, the wafer is exposed to post-exposure baking and then is developed and hard-baked to develop the photoresist pattern.
A substrate 10 having a conductive layer 12 deposited thereon is shown in FIG. 1. Frequently, one or multiple pin holes 14 extends through the conductive layer 12 into the wafer 10 for various purposes such as testing or proper alignment of the wafer 10 prior to processing, for example. A layer of photoresist 16 is deposited on the conductive layer 12 and then is typically subjected to a soft-bake curing step. Next, the photoresist 16 is subjected to an alignment and exposure step in which the photoresist 16 is exposed to light through a reticle or mask (not shown) to superimpose the circuit pattern in the reticle or mask onto the photoresist 16 by cross-linking the photoresist 16 along the areas of light exposure. Finally, the underlying conductive layer 12 is etched around the etchant-resistant, cross-linked photoresist to form the desired circuit pattern in the conductive layer 12.
The photoresist-deposition step is typically carried out in a coater cup (not shown) which is open to atmospheric pressure in the semiconductor fabrication facility. Accordingly, in the coater cup the photoresist 16 is layered over the conductive layer 12 under atmospheric pressure and extends over the pin holes 14, as shown in FIG. 1. During this step, air becomes trapped in the pin holes 14. During the subsequent soft-bake step which is carried out to cure the photoresist 16, the heated air trapped in the pin holes 14 expands against the overlying photoresist 16, pushing the photoresist 16 upwardly and forming air bubbles 18 above the respective pin holes 14, as shown in FIG. 2. These air bubbles 18 interfere with subsequent processing of the substrate 10, particularly the alignment and exposure process which is carried out after the soft bake curing step to superimpose the circuit pattern image from the mask or reticle onto the photoresist 16. Accordingly, an apparatus and method is needed for carrying out the photoresist-coating step in such a manner as to eliminate the formation of air bubbles in the photoresist during the soft bake photoresist-curing step.
An object of the present invention is to provide an apparatus and method for the bubble-free application of a resin to a substrate.
Another object of the present invention is to provide an apparatus and method which is suitably adapted for applying a photoresist to a wafer in such a manner as to eliminate the formation of air pockets in the wafer beneath the photoresist.
Still another object of the present invention is to provide an apparatus and method which is suitable for preventing the formation of air bubbles in or beneath a layer of photoresist during a soft-bake curing step of photolithography.
Yet another object of the present invention is to provide an apparatus and method which may have application to various industries in the bubble-free application of a resin to a substrate.
A still further object of the present invention is to provide a method for the bubble-free application of a resin to a substrate, which method includes applying the resin to the substrate under vacuum pressure.
Yet another object of the present invention is to provide an apparatus which is suitable for the bubble-free application of a resin to a substrate, which apparatus includes an airtight chamber for receiving the substrate and a resin supply dispenser for dispensing the resin onto the substrate.